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r18ds0004ej0102 rev. 1.02 page 1 of 26 jul.09, 2013 datasheet raa23040x 3-ch step-down switching regulator + 1-ch ldo description the raa23040x is a power supply ic that has 3-ch st ep-down switching regulator containing power mosfet s and 1-ch ldo. features ? switching regulator (ch1, ch3, ch4) ? synchronous rectification type step-down circuit ? integrated power mosfets ? internal phase compensator ? power good function (ch1) ? low power mode (ch1, ch3 and ch4 operate at low frequency and redu ce the power consumption of the ic.) ? switching frequency: 1.3 mhz to 2 mhz (variable) ? internal timer-latch-type short-circuit protector ? ldo (ch2) ? internal over current protector (foldback-current l imiting) ? common part ? independent on/off control for each channel ? internal digital soft-start function (adjustable so ft-start time) ? internal discharge circuit ? internal timer-latch-type thermal shutdown circuit (shutdown temperature: 150c or higher) ? internal recovery-type under voltage lockout circui t pkg and packing part no. package packing raa23040xgnp 32-pin vqfn embossed taping. 4,000pcs/ reel RAA23040XGFT 32-pin tqfp tray. 1,250pcs/inner box r18ds0004ej0102 rev.1.02 jul.09, 2013
r18ds0004ej0102 rev. 1.02 page 2 of 26 jul.09, 2013 product lineup table the following 9 products are developed based on out put voltage. ch raa230401 raa230402 raa230403 raa230404 raa230405 raa230406 raa230407 raa230408 raa230409 1 1.8 v 2.5 v 3.0 v 3.3 v 1.8 v 2.5 v 3.0 v 3.3 v adj ustable 2 3 3.3 v adjustable 4 output voltage is selectable. 1.2 v preset voltage by internal resistor or adjustable by external resi stor. note: ch1, ch2: raa230401 to raa230408 output prese t voltage by internal resistor. raa230409 outputs a djustable voltage by external resistor. ch3: raa230401 to raa230404 output preset voltage by internal resistor. raa230405 to raa230409 output adjustable voltage by external resistor. ch4: all products have switchable output voltage b etween 1.2 v preset voltage by internal resistor an d adjustable voltage by external resistor. constitution example ? input voltage: 2.5 v to 5.5 v ch type power mosfet output voltage maximum output current example 1 synchronous rectification type step-down circuit (current mode) integrated 0.9 v to vin 0.8 v 500 ma 2 ldo ? 0.9 v to vin 0.8 v 100 ma 3 synchronous rectification type step-down circuit (current mode) integrated 0.9 v to vin 0.8 v 1500 ma 4 synchronous rectification type step-down circuit (current mode) integrated 0.9 v to vin 0.8 v 1500 ma
r18ds0004ej0102 rev. 1.02 page 3 of 26 jul.09, 2013 application circuit example ch1 to ch3: preset output voltage by internal resis tor. ch4: preset output voltage by internal resistor is selected. (ctl4 = h) scp shdnb1 shdnb2 shdnb3 rt av dd ii1 + + ? 0.8v + + ? 0.8v e/a1 phase compensator phase compensator phase compensator oscillator osc under voltage lockout circuit uvlo shdnb0 control pg1 short-circuit protection circuit scp out2 input voltage control-ic agnd test1 vp in2 ldo ss ii3 e/a3 ch3 out ii4 ch4 out 1.2v pgnd4 lout4 ch4 out discharge control vp in4 shdnb4 ii2 test2 save ctl4 control circuit ? on/off ? soft start ? discharge test circuit avdd + + ? 0.8v e/a4 ch1 out thermal shutdown circuit tsd reference voltage v ref internal power supply v reg 3.3v pgnd3 lout3 ch3 out discharge control vp in3 discharge control output control (current mode /current limit) output control (current mode /current limit) output control (current mode /current limit) 1.8v 2.5v 3.0v 3.3v pgnd1 lout1 ch1 out discharge control vp in1 1.8v 2.5v 3.0v 3.3v ch2 out v reg v ref v reg
r18ds0004ej0102 rev. 1.02 page 4 of 26 jul.09, 2013 ch1 to ch3: adjustable output voltage by external r esistor. ch4: adjustable output voltage by external resistor is selected. (ctl4 = l) scp shdnb1 shdnb2 shdnb3 rt av dd ii1 + + ? 0.8v + + ? 0.8v e/a1 shdnb0 control pg1 out2 input voltage control-ic agnd test1 vp in2 ldo ss ii3 e/a3 ch3 out ii4 0.9v~av dd pgnd4 lout4 ch4 out discharge control vp in4 shdnb4 ii2 test2 save ctl4 avdd + + ? 0.8v e/a4 ch4 out ch1 out 0.9v~av dd pgnd3 lout3 ch3 out discharge control vp in3 discharge control 0.9v~av dd pgnd1 lout1 ch1 out discharge control vp in1 0.9v~ av dd -0.5v ch2 out phase compensator phase compensator phase compensator oscillator osc under voltage lockout circuit uvlo short-circuit protection circuit scp control circuit ? on/off ? soft start ? discharge test circuit thermal shutdown circuit tsd output control (current mode /current limit) output control (current mode /current limit) output control (current mode /current limit) reference voltage v ref internal power supply v reg v reg v ref v reg
r18ds0004ej0102 rev. 1.02 page 5 of 26 jul.09, 2013 pin configuration 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 rt shdnb3 save ss shdnb2 shdnb1 shdnb0 test1 vp in2 test2 (top view) agnd av dd out2 lout1 vp in1 pgnd1 ii1 pg1 ctl4 scp ii2 shdnb4 lout3 vp in3 pgnd3 ii3 ii4 pgnd4 vp in4 lout4 32 31 30 29 28 27 26 16 9 10 11 12 13 14 15 v reg v ref rt shbnd3 save ss shbnd2 shbnd1 shbnd0 test1 vp in2 v reg test2 agnd av dd v ref out2 lout1 vp in1 pgnd1 ii1 pg1 ctl4 scp ii2 shbnd4 lout3 vp in3 pgnd3 ii3 ii 4 pgnd4 vp in4 lout4 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 (top view) exposed pad 32 - pin tqfp 32 - pin vqfn
r18ds0004ej0102 rev. 1.02 page 6 of 26 jul.09, 2013 pin function pin no. symbol i/o function 1 lout1 output inductor connection for ch1 2 vp in1 power supply output stage power input of ch1 3 pgnd1 ground power ground 4 ii1 input inverted input for error amplifier of c h1 5 pg1 output power-good output of ch1 (open-drain) 6 ctl4 input output voltage setting mode of ch4 7 scp ? capacitor connection pin for timer latch 8 ii2 input inverted input for error amplifier of c h2 9 vp in2 power supply output stage power input of ch2 10 out2 output output of ch2 11 v ref output reference voltage output 12 av dd power supply analog block power supply 13 agnd ground analog ground 14 test2 ? test pin 2 (connect to v reg ) 15 v reg output internal power supply output 16 test1 ? test pin 1 (connect to agnd) 17 lout3 output inductor connection for ch3 18 vp in3 power supply output stage power input of ch3 19 pgnd3 ground power ground 20 ii3 input inverted input for error amplifier of ch3 21 ii4 input inverted input for error amplifier of ch4 22 pgnd4 ground power ground 23 vp in4 power supply output stage power input of ch4 24 lout4 output inductor connection for ch4 25 shdnb4 input output on/off of ch4 26 shdnb3 input output on/off of ch3 27 save input low power operation mode setting pin 28 ss ? resistance connection for soft start time s etting 29 rt ? resistance connection for triangular wave g eneration 30 shdnb2 input output on/off of ch2 31 shdnb1 input output on/off of ch1 32 shdnb0 input output on/off of ic
r18ds0004ej0102 rev. 1.02 page 7 of 26 jul.09, 2013 absolute maximum ratings (unless otherwise specified, t a = 25c) parameter symbol ratings unit condition analog power supply (av dd pin) av dd ?0.5 to +6.5 v av dd vp in pin applied voltage vp in ?0.5 to +6.5 v vp in1 to vp in4 shdnb pin applied voltage v shdnb ?0.5 to +6.5 v shdnb0 to shdnb4 ctl4 pin applied voltage v ctl4 ?0.5 to +6.5 v ctl4 save pin applied voltage v save ?0.5 to +6.5 v save pg pin applied voltage v pg ?0.5 to +6.5 v pg1 ii pin applied voltage v ii ?0.5 to +6.5 v ii1 to ii4 vp in1 pin sink current (peak) ip in1(peak)? 600 ma vp in1 vp in2 pin sink current (dc) ip in2(dc)? 200 ma vp in2 vp in3 pin sink current (peak) ip in3(peak)? 2000 ma vp in3 vp in4 pin sink current (peak) ip in4(peak)? 2000 ma vp in4 lout1 pin output source current (peak) i lo1(peak)+ 600 ma lout1 out2 pin output source current (dc) i o2(dc)+ 200 ma out2 lout3 pin output source current (peak) i lo3(peak)+ 2000 ma lout3 lout4 pin output source current (peak) i lo4(peak)+ 2000 ma lout4 lout1, out2, lout3, lout4 pin output source current (dc) i lo1,o2,lo3,4(dc)? 100 ma when discharge circuit is operation. total power dissipation p t vqfn: 1850 *1 mw t a +25c tqfp: 2100 1 operating ambient temperature t a ?40 to +85 c junction temperature t j ?40 to +150 c storage temperature t stg ?55 to +150 c note: *1 this is the value at t a +25c. at t a > +25c, the total power dissipation is derated by ?18.5 mw/ c (vqfn) or -21mw/c (lqfp). board specification: vqfn:4-layers glass epoxy boar d. 76.2mm x 114.3mm x 1.664mm. copper coverage area: 50% (top and botto m layers)/95% ( layers 2 and 3). tqfp:4-layers glass epoxy b oard. 80mm x 80mm x 1.6mm. renesas evaluation board for the case of that exposed pad is not soldered to gnd copper pattern on board. caution: product quality may suffer if the absolute maximum rating is exceeded even momentarily for an y parameter. that is, the absolute maximum ratings are rated val ues at which the product is on the verge of sufferi ng physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
r18ds0004ej0102 rev. 1.02 page 8 of 26 jul.09, 2013 recommended operating condition (unless otherwise specified, t a = 25c) parameter symbol min typ max unit condition analog power supply voltage (av dd pin) av dd 2.5 5.0 5.5 v av dd vp in pin applied voltage vp in ? av dd ? v vp in1 to vp in4 shdnb pin applied voltage v shdnb 0 ? av dd v shdnb0 to shdnb4 ctl4 pin applied voltage v ctl4 0 ? av dd v ctl4 save pin applied voltage v save 0 ? av dd v save pg pin applied voltage v pg 0 ? av dd v pg1 ii pin applied voltage v ii 0 ? av dd v ii1 to ii4 oscillation frequency f osc 1300 ? 2200 khz oscillator timing resistance r t ? 10 ? k r t soft start resistance r ss ? 1000 ? k ss scp pin capacitance c scp ? 0.1 ? f scp v ref pin capacitance c ref ? 1.0 ? f v ref v reg pin capacitance c reg ? 1.0 ? f v reg operating junction temperature t jo ?40 ? +125 c
r18ds0004ej0102 rev. 1.02 page 9 of 26 jul.09, 2013 electrical characteristics (unless otherwise specified, t a = 25c, av dd = vp in1 to vp in4 = 5.0 v, f osc = 2 mhz) parameter symbol min typ max unit condition total standby current i dd(stnby) ? 1 2 a ai dd +ip in1 +ip in2 +ip in3 +ip in4 shdnb0 to shdnb4 = agnd circuit operation current 1 i dd1 ? 1.2 2 ma ai dd , shdnb0 = av dd shdnb1 to shdnb4 = agnd save = gnd circuit operation current 2 i dd2 ? 0.7 1.0 ma ai dd , shdnb0 = av dd shdnb1 to shdnb4 = agnd save = av dd reference voltage block (v ref ) reference voltage v ref 0.98 1.00 1.02 v i ref = 0ma temperature characteristic ? 0.5 ? % t a = ?10c to +60c internal power supply block (v reg ) internal power supply voltage v reg 2.3 2.4 2.5 v i reg = 0ma under voltage lock out circuit (uvlo) operation start voltage during rise time av dd(l-h) 1.9 2.1 2.3 v av dd pin voltage is detected operation stop voltage av dd(h-l) 1.7 1.9 2.1 v av dd pin voltage is detected short-circuit protection circuit (scp) ii1 input detection voltage (ch1) v th(ii)1 65 75 85 % ii1 pin, ratio to the output voltage ii3 input detection voltage (ch3) v th(ii)3 65 75 85 % ii3 pin, ratio to the output voltage ii4 input detection voltage (ch4) v th(ii)4 65 75 85 % ii4 pin, ratio to the output voltage dly detection voltage v th(dly) 0.6 0.9 1.2 v scp pin short-circuit source current i out 0.6 1.0 1.4 a oscillation block frequency setting accuracy f osc ?10 ? +10 % r t = 10k input stability ? f osc ?3 ? +3 % av dd = 2.5v to 5.5v soft start block soft start time t ss ? 2.0 4.0 ms ch1 to ch4, r ss = 1000k pwm block maximum duty d max.(pwm) ? 100 ? % ch1, ch3, ch4 output voltage accuracy (with resistor inside) ch1 output voltage accuracy v out1 ?2 ? +2 % i o1 = 10ma, (with internal resistor) ch2 output voltage accuracy v out2 ?1 ? +1 % i o2 = 10ma, (with internal resistor) ch3 output voltage accuracy v out3 ?2 ? +2 % i o3 = 200ma, (with internal resistor) ch4 output voltage accuracy v out4 ?2 ? +2 % i o4 = 200ma, (with internal resistor) e/a block (with resistor outside) e/a 1 input threshold voltage v ith1 0.784 0.800 0.816 v including input offset, (with external resistor) e/a 2 input threshold voltage v ith2 0.792 0.800 0.808 v including input offset, (with external resistor) e/a 3 input threshold voltage v ith3 0.784 0.800 0.816 v including input offset, (with external resistor) e/a 4 input threshold voltage v ith4 0.784 0.800 0.816 v including input offset, (with external resistor) output block (ch1) p-ch output on resistance r on-p1 ? 0.4 0.6 i o = 100ma n-ch output on resistance r on-n1 ? 0.4 0.6 i o = ?100ma output block (ch3, ch4) p-ch output on resistance r on-p1 ? 0.4 0.6 i o = 100ma n-ch output on resistance r on-n1 ? 0.4 0.6 i o = ?100ma discharging circuit block output on resistance1 r ondc1 ? 100 200 ch1, ch3, ch4, i dc = 20ma output on resistance2 r ondc2 ? 200 400 ch2, i dc = 20ma
r18ds0004ej0102 rev. 1.02 page 10 of 26 jul.09, 2013 electrical characteristics (cont.) (unless otherwise specified, t a = 25c, av dd = vp in1 to vp in4 = 5.0 v, f osc = 2 mhz) parameter symbol min typ max unit condition series regulator block (ch2) the voltage between the input and output v dif2 0.5 ? ? v i o2 = 20ma input regulation reg in2 ? ? 50 mv i o2 = 20ma, vp in2 > vout2+0.5v load regulation reg l2 ? ? 50 mv i o2 = 1ma to 100ma output short-circuit current i o2short ? 80 ? ma out2=agnd peak output current i o2peak 150 ? ? ma t.b.d. power-good circuit block (ch1) threshold voltage v th(pg)1 86 90 94 % pg1 = "hiz" "l", "l" "hiz" detection of ii1 pin ratio to the output voltage pg pin output voltage v pg ? ? 0.1 v i pg? = 0.1ma pg pin leakage current i leak-pg ? ? 1 a shdnb0 to shdnb4 = agnd delay time t dly-pg ? ? 2 ms time from detecting of output startup until change form l to hiz on pg pin on/off controller block threshold voltage v th 0.8 ? 2.0 v shdnb0 to shdnb4, save input pull-down resistance r ind 200 400 700 k shdnb0 to shdnb4, save
r18ds0004ej0102 rev. 1.02 page 11 of 26 jul.09, 2013 typical performance characteristics (unless otherwise specified, t a = 25c, av dd = vp in1 to vp in4 = 5.0 v, f osc = 2 mhz) efficiency vs. output current c h 3 efficiency vout 3 = 2.5 v c h 4 efficiency vout 4 = 1.2 v ch1 efficiency vout1 = 3.3v c h 3 efficiency vout 3 = 3.3v 2mhz save(0.3mhz) 2mhz save(0.3mhz) 2mhz save(0.3mhz) 2mhz save(0.3mhz)
r18ds0004ej0102 rev. 1.02 page 12 of 26 jul.09, 2013 start-up waveforms example 1 ch1(3.3v) ->ch2(3.3v) ->ch3(2.5v) ->ch4(1.2v) configuration waveform example 2 ch1(1.2v) ->ch2(1.2v) ->ch3(1.2v) ->ch4(1.2v) configuration waveform shdnb pins have pull-down resistors (400k ). please make sure that input voltage divided by external resistor on shdnb pins shall not be lower than 1.4v .
r18ds0004ej0102 rev. 1.02 page 13 of 26 jul.09, 2013 ic surface temperature vs. time ? all channel operating (normal mode) ? vin=5v ? ch1: 3.3 v, 0.5 a ch2: 3.3 v, 0.1a ch3: 3.3 v, 1.5 a ch4: 1.2 v, 1.5 a ? t a =25c ? measured on renesas evaluation board temperature derating curve 0 10 20 30 40 50 60 70 80 90 0 5 10 15 20 25 30 temperature (oc) time (min.) ic surface temperature vs. time vqfn tqfp 0 250 500 750 1000 1250 1500 1750 2000 2250 0 25 50 75 100 125 pt (w) t a ( c ) tqfp vqfn
r18ds0004ej0102 rev. 1.02 page 14 of 26 jul.09, 2013 load transient waveforms ch1 normal mode, vout1 = 3.3v l1 = 4.7 h, cin1 = 10 f, cout1 = 22 f iout1 200ma/div. iout3 500ma/div. iout4 500ma/div. vout1 200mv/div. vout3 200mv/div. vout4 100mv/div. iout3 500ma/div. vout3 200mv/div. 500 s/div. 100 s/div. 100 s/div. 100 s/div. 100 s/div. iout1 = 10ma iout1 = 500ma iout2 50ma/div. vout2 100mv/div. iout2 = 0ma iout2 = 100ma iout3 = 10ma iout3 = 1500ma iout3 = 10ma iout3 = 1500ma iout4 = 10ma iout4 = 1500ma ch2, vout2 = 3.3v cin2 = 10 f, cout2 = 2.2 f ch3 normal mode, vout3 = 3.3v l3 = 2.2 h, cin3 = 10 f, cout3 = 22 f ch3 normal mode, vout3 = 2.5v l3 = 2.2 h, cin3 = 10 f, cout3 = 22 f ch4 normal mode, vout4 = 1.2v l4 = 2.2uh, cin4 = 10uf, cout4 = 22uf
r18ds0004ej0102 rev. 1.02 page 15 of 26 jul.09, 2013 control block shdnb0 to shdnb4: on/off setting shdnb0 shdnb1 shdnb2 shdnb3 shdnb4 common circuit ch1 ch2 ch3 ch4 l l or h l or h l or h l or h off off off off off h l l l l on off off off off h h l l l on on off off off h l h l l on off on off off h l l h l on off off on off h l l l h on off off off on h h h h h on on on on on note: l: low level, h: high level common circuit: reference voltage block, internal p ower supply block, oscillator block and so forth off: circuit stand-by, on: circuit operation status save: ic low power mode setting save ic operation l normal operation (ch1, ch3, ch4 operate at oscillation frequency set by rt) h low power mode operation (ch1, ch3, ch4 operate at 15% oscillation frequency of normal operation) note: l: low level, h: high level ctl4: ch4 output voltage setting ctl4 ch4 output voltage setting l external resistor setting h internal resistor setting (fixed 1.2 v) note: l: low level, h: high level
r18ds0004ej0102 rev. 1.02 page 16 of 26 jul.09, 2013 output status v reg , v ref pin status shdnb0 v reg v ref l agnd agnd h 2.4 v 1.0 v note: l: low level, h: high level ch1 to ch4 output pin status shdnb0 shdnb1 to shdnb4 ch1 ch2 ch3 ch4 lout1 out2 lout3 lout4 l l or h hiz (discharge circuit, off) agnd (discharge circuit, on) hiz (discharge circuit, off) h l pgnd (discharge circuit, on) agnd (discharge circuit, on) pgnd (discharge circuit, on) h pulse (vp in1 or pgnd) ch2 (set voltage) pulse (vp in3 or pgnd) pulse (vp in4 or pgnd) note: l: low level, h: high level, hiz: high impeda nce pg1 pin status ic operation status pg1 output status shdnb0 = l hiz shdnb0 = h the ch1 output voltage is under 90% of t he set voltage l the ch1 output voltage is over 90% of the set volta ge hiz note: l: low level, hiz: high impedance caution: when using power good (pg1 pin), connect i t to ch1 output.
r18ds0004ej0102 rev. 1.02 page 17 of 26 jul.09, 2013 timing chart av dd shdnb0 ch1 out shdnb1 ch2 out shdnb2 ch3 out shdnb3 ? input ? output shdnb4 ch4 out 90% 90% 2.4 v 1.0 v the output voltage of each channel can be turned on/off individually. when shdnb0 is set to off, the discharge circuit doesn't operate. (naturally discharge) pg1 (open) pg1 (connect to ch1 out) ch1 out hiz hiz hiz hiz v reg v ref
r18ds0004ej0102 rev. 1.02 page 18 of 26 jul.09, 2013 operation of each block (overview) short-circuit protection circuit (ch1, ch3 and ch4) when the voltage of ch1, ch3 and ch4 drops, the vol tage of the e/a inverted input pin to which the out put is being fed back also drops. if this inverted input pin voltage falls below the input detection voltage of the sho rt-circuit protection circuit (under 75% of output voltage), the timer ci rcuit starts operating and the capacitor connected to the scp pin (cscp) starts charging. when the voltage of the cap acitor connected to the scp pin reaches 0.9 v (typ. ), all the outputs are latched to off. at this time, common ci rcuits (such as the reference voltage block, intern al power supply block, and oscillator, etc.) continue operating. as long as the voltage of any of the e/a inverted i nput pins of ch1 to ch4 is below the input detectio n voltage of the short-circuit protection circuit, the capacitor con nected to the scp pin continues charging. when the short-circuit protection circuit is operat ing, to reset the latch circuit, either change the level of the shdnb0 pin from high to low or drop the level of the power supply voltage (av dd ) to the level below the operation stop voltage of the under voltage lockout circuit (1.7 v to 2.1 v). ? timing chart (when ch1 is short circuited) the input detection voltage 0.9v scp shdnb0 shdnb1 (1) (2) (3) ii1 (1) (1) at starting ? a short circuit will not be detected while a channe l is undergoing a soft start (that is, short-circui t protection is not triggered). if a short circuit occurs while a c hannel is operating, short-circuit protection will start after the soft start time elapses following startup. ? if a short circuit occurs in a channel that is oper ating while another channel is being soft-started, short-circuit protection will start immediately. (2) short-circuit protection operation ? if a short circuit is detected in any of channel 1, 3 and 4 (channels whose ii pin voltage is lower th an the input detection voltage except channels that are being so ft-started), the capacitor connected to the scp pin starts charging. if short circuits occur in multiple chann els, the capacitor connected to the scp pin continu es to charge until the short-circuit state of all channels is ca nceled (that is, until the ii pin voltage is restor ed over the input detection voltage). ? once the scp pin voltage reaches 0.9 v, output from all channels stops (and is latched to off). ? common circuits (such as the reference voltage bloc k, internal power supply block, and oscillator, etc .) continue operating. (3) cancelling short-circuit protection ? to reset the latch circuit, either change the level of the shdnb0 pin from high to low, or drop the le vel of the power supply voltage (av dd ) to the operation stop voltage of the under voltag e lockout circuit (1.7 v to 2.1 v).
r18ds0004ej0102 rev. 1.02 page 19 of 26 jul.09, 2013 thermal shutdown circuit (timer latch type) after overheating has been detected (shutdown tempe rature: 150c or higher), the timer circuit starts operating and the capacitor connected to the scp pin (cscp) starts ch arging. when the voltage of the capacitor connected to the scp pin reaches 0.9 v (typ.), all the outputs are latched t o off (as same as scp). common circuits (such as th e reference voltage block, internal power supply block, and osc illator, etc.) continue operating. when the thermal shutdown circuit is operating, to reset the latch circuit, either change the level of the shdnb0 pin from high to low, or drop the level of the power su pply voltage (av dd ) to the operation stop voltage of the under voltage lockout circuit (1.7 v to 2.1 v). under voltage lockout circuit (auto recovery type) (1) under voltage lockout operation when the power supply voltage (av dd ) falls to the operation stop voltage (1.7 v to 2.1 v), output from all channels stops. common circuits (such as the reference volta ge block, internal power supply block, and oscillat or, etc.) continue operating. (2) restoring output once av dd voltage is restored to the operation start voltage (1.9 v to 2.3 v), the under voltage lockout operat ion is canceled and output automatically resumes. the outp ut voltage cannot be restored while the under volta ge lockout circuit is operating, not even by manipulating the shdnb0 pin. current limiting ch1, ch3, and ch4 operate under the current control mode. if an overcurrent occurs, the current is lim ited on a pulse-by- pulse basis. if the current sensor detects an overc urrent, the current is limited and the switching op eration of the power mosfet in the output stage stops until the next cyc le. when the current is limited, the output voltage of the channel on which the overcurrent occurred drops . if the ii pin voltage falls below the input detection voltage, th e short-circuit protection circuit starts operating . reference data (unless otherwise specified, t a = 25c, av dd = vp in1 to vp in4 = 5.0 v, f osc = 2 mhz) item symbol min typ max unit measurement condition current limit value ch1 current limet i lim1 ? 1.6 ? a ch1out = 3.3v ch3, ch4 current limet 1 i lim34_1 ? 2.6 ? a ch3out = ch4out = 3.3v ch3, ch4 current limet 2 i lim34_2 ? 2.1 ? a ch3out = ch4out = 1.2v note: these data are for reference and not guarant eed as specifications. over current protection (ch2) ch2 have a fold back type current protection circui t. if load current exceeds 150 ma, protection opera tion is started and load current is limited (output short-circuit curre nt: 80 ma). low power mode this ic has the low power mode. by setting save pin into a high level, the oscillation frequency of a switching regulator (ch1, ch3, ch4) is dropped on 15% oscilla tion frequency of normal operation, and the power c onsumption of the ic is reduced. when switching to the low power mode, please switch the mode in a condition that the output current of a switching regulator (ch1, ch3, ch4) is below 100 ma. please be cautious of increasing the ripple voltage of each channel at the low power mode.
r18ds0004ej0102 rev. 1.02 page 20 of 26 jul.09, 2013 advance on designing setting output voltage (when the output voltage is set by external resistor) the output voltage settings are shown in the figure s below. the output voltage can be calculated by us ing the equations shown in these figures. [setting output voltage of ch1 to ch4 by external resistor] 0.8v(typ.) v out (output voltage) r1 r2 e/a1, e/a2, e/a3, e/a4 v out = (1+r1/r2) 0.8 ? + setting oscillation frequency the oscillation frequency (f osc ) can be arbitrarily set by the timing resistance ( r t ) connected to the rt pin. approximate equation: f osc [mhz] = ?0.107 r t [k ] + 3.05 calculating the soft start time the soft start time (t ss ) can be arbitrarily set by the resistance (r ss ) connected to the ss pin. approximate equation: t ss [ms] = 1.8 r ss [m ] + 0.24 note: soft start time is the same by all channels. calculating the delay time of the short-circuit pro tection circuit the following approximate expression is for calcula ting the delay time t dly of the short-circuit protection circuit. the delay time of the short-circuit protection circ uit (t dly ) can be arbitrarily set by the capacitor (c scp ) connected to the scp pin. approximate equation: t dly [s] = 0.9 c scp [ f] pin handling when short-circuit protection circuit is not used when the short-circuit protection circuit is not us ed, connect the scp pin to the agnd pin. at this ti me, closely monitor heating because the overheat protection cir cuit does not operate.
r18ds0004ej0102 rev. 1.02 page 21 of 26 jul.09, 2013 handling of pins when not used connect unused pins as below. always connect avdd pin, vpin1 pin, vpin2 pin, vpin 3 pin and vpin4 pin with power supplies, and connec t pgnd1 pin, pgnd3 pin, pgnd4 pin and agnd with the g round. when ch1 is not used:. pin number pin name connection 31 shdnb1 agnd 2 vp in1 av dd , or vp in of other ch 1 lout1 pgnd 3 pgnd1 pgnd 4 ii1 agnd when ch2 is not used: pin number pin name connection 30 shdnb2 agnd 9 vp in2 av dd , or vp in of other ch 10 out2 agnd 8 ii2 agnd when ch3 is not used: pin number pin name connection 26 shdnb3 agnd 18 vp in3 av dd , or vp in of other ch 17 lout3 pgnd 19 pgnd3 pgnd 20 ii3 agnd when ch4 is not used: pin number pin name connection 25 shdnb4 agnd 23 vp in4 av dd , or vp in of other ch 24 lout4 pgnd 22 pgnd4 pgnd 21 ii4 agnd 6 ctl4 agnd when pg1 pin is not used pin number pin name connection 5 pg1 agnd
r18ds0004ej0102 rev. 1.02 page 22 of 26 jul.09, 2013 inductor selection it is recommended to choose a inductor which rippl e current ( ? il) becomes 20 to 40 % of iout(max). when ? il increases, inductor current peak raises, so ripp le of vout gets larger and power loss increases. b ut, large inductor is required to lower ? il. ? il can be calculated by an equation below. ? il = (vin-vout) / l x vout / vin x 1 / fsw fsw : switching frequency of dcdc, 1.3mhz to 2mhz peak current of inductor (ilpeak) can be calculated by an equation below. ilpeak = iout(max) + ? il / 2 choose a inductor which saturation current is highe r than ilpeak . inductor example note i temp : rated current by temperature rising i sat : rated current by inductance loss these inductors are examples. about inductor deta il, contact each manufacturer. ch output current inductor manufacturer inductance (uh) i temp (a) i sat (a) size (lxwxt, mm) ch1 less than 0.5a cpl2512t4r7m tdk 4.7 0.65 0.65 2.5x1.5x1.2 nrs2012t4r7mgj taiyo yuden 4.7 0.82 0.76 2x2x1.2 74479787247a wurth 4.7 1.5 0.27 2.5x2x1 744028004 wurth 4.7 0.85 0.7 2.8x2.8x1.1 ch3 ch4 less than 1a vls201612et-2r2m tdk 2.2 1.15 1.05 2x1.6x1.2 nrs2012t2r2mgj taiyo yuden 2.2 1.37 1.35 2x2x1.2 744029002 wurth 2.2 1.5 1.15 2.8x2.8x1.35 1a to 1.5a lqh44pn2r2mp0 murata 2.2 1.8 2.5 4x4x1.6 5 nrs4018t2r2mdgj taiyo yuden 2.2 2.2 3 4x4x1.8 744025002 wurth 2.2 1.8 2.4 2.8x2.8x2.8
r18ds0004ej0102 rev. 1.02 page 23 of 26 jul.09, 2013 output capacitor selection each channel of raa23040x has a phase compensation circuit which is optimized to each operation. in or der to operate stably with the phase compensation, connect the out put capacitor : switching regulator (ch1, ch3, ch4) : over 22uf ldo (ch2) : over 2.2uf ceramic capacitor can be used for output capacitor. it has low esr, so vout ripple is decreased. vout ripple ( ? vrpl) can be calculated by an equation below. ? vrpl = ? il x (esr + 1 / (8 x cout x fsw )) input capacitor selection recommended input capacitor of switching regulator can be calculated by an equation below. connect the capacitor that value is over calculated one. cin > (iout(max) x vout / vin) / ( ? vin x fsw) about ldo, connect the capacitor that value is over 1uf.
r18ds0004ej0102 rev. 1.02 page 24 of 26 jul.09, 2013 notes on use condition where protection circuits do not operate when the scp pin is connected to the agnd pin, the short-circuit protection circuit and thermal shutdo wn circuit do not operate. pin connection be sure to apply the same voltage to av dd pin and vp in pin (except vp in2 ). vp in2 input voltage vp in2 input voltage should be same or less than av dd . pg1 connection when using power good (pg1 pin), connect it to ch1 output. if pg1 is connected to av dd , pg1 outputs high (av dd ) when shdnb0 is low (because pg1 is high impedance w hen shdnb0 is low). actual pattern wiring to actually perform pattern wiring, separate the gr ound of the control signals from the ground of the power signals, so that these signals do not have a common impedance a s much as possible. in addition, lower the high-fre quency impedance by using a capacitor, so that noise is no t superimposed on the v ref pin, v reg pin. connection of exposed pad (only tqfp package) tqfp package has an exposed pad on the bottom to im prove radiation performance. on the mounting board, connect this exposed pad to agnd. fixed usage of control input pin when using fixed input pins shdnb0 to shdnb4, ctl4 and save input pins, connect each input to the pins listed below. input pin connect pin fixed to low level fixed to high level shdnb0 agnd av dd shdnb1 agnd av dd shdnb2 agnd av dd shdnb3 agnd av dd shdnb4 agnd av dd ctl4 agnd av dd save agnd av dd
r18ds0004ej0102 rev. 1.02 page 25 of 26 jul.09, 2013 package dimensions 32-pin vqfn 5 mm 5 mm 0.4 mm pitch jeita package code renesas code previous code mass[typ.] p-vqfn32-5x5-0.40 pvqn0032la-a ? 0.05g d a e h e b b s y 1 z d h d z e s y c 1 a 1 a 2 a c a s s ab s m t 4x 17 24 2532 1 8 9 16 b 1 l p e b min reference symbol dimension in millimeters nom max d ea a 1 b 1 y 1 a 2 l p h d h e z d z e be xy c 1 c t 5.0 5.0 0.89 0.95 0.005 0.02 0.04 0.13 0.18 0.23 0.16 0.4 0.17 0.22 0.25 0.20 0.05 0.05 0.2 0.2 0.50 0.60 5.2 5.2 1.1 1.1 0.70
r18ds0004ej0102 rev. 1.02 page 26 of 26 jul.09, 2013 32-pin tqfp 7 mm 7 mm 0.8 mm pitch
all trademarks and registered trademarks are the pr operty of their respective owners. c - 1 revision history raa23040x data sheet rev. date description page summary 1.01 oct 18, 2012 - first edition issued 1.02 jul 09, 2013 1 changed package name from lqfp to tqfp. added packing unit. 5 added pin configuration of 32-pin tqfp. 7 added total power dissipation and board specifi cation. 9 changed short-circuit source current from min 0.7ua to 0.6ua and max 1.3ua to 1.4ua. 10 changed output short-circuit current from typ 40ma to 80ma. added condition of input regulation, load regulatio n and output short-circuit current. 12 added start-up waveforms. 13 added input voltage vin condition. changed output v oltage/current condition. added tqfp product?s data. added temperature derati ng curve. 16 changed output pin status of ch2 at shdnb0=l f rom hiz to gnd. 19 added reference data of current limit value. changed output short-circuit current of over curren t protection (ch2) from typ 40ma to 80ma. 21 added handling of pins when not use. 22 added inductor selection 23 added output capacitor selection and input cap acitor selection. 24 added connection of exposed pad. 26 added package dimensions of tqfp package.
notes for cmos devices (1) voltage application waveform at input pin: wav eform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when t he input level passes through the area between vil (ma x) and vih (min). (2) handling of unused input pins: unconnected cmo s device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to no ise, etc., causing malfunction. cmos devices behave diff erently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resistor if there is a possibility that it will be an output p in. all handling related to unused pins must be judged sepa rately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fiel d, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrad e the device operation. steps must be taken to stop generation of static electricity as much as possibl e, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up stat ic electricity. semiconductor devices must be store d and transported in an anti-static container, static shi elding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mou nted semiconductor devices. (4) status before initialization: power-on does no t necessarily define the initial status of a mos device. immediately after the power source is turne d on, devices with reset functions have not yet bee n initialized. hence, power-on does not guarantee out put pin levels, i/o settings or contents of registe rs. a device is not initialized until the reset signal is received. a reset operation must be executed immed iately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the interna l operation and external interface, as a rule, switch on the external power supply after switching on th e internal power supply. when switching the power sup ply off, as a rule, switch off the external power supply and then the internal power supply. use of t he reverse power on/off sequences may result in the application of an overvoltage to the internal eleme nts of the device, causing malfunction and degradat ion of internal elements due to the passage of an abnor mal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) input of signal during power off state: do not input signals or an i/o pull-up power supply while the device is not powered. the current inject ion that results from input of such a signal or i/o pull- up power supply may cause malfunction and the abnor mal current that passes in the device at this time may cause degradation of internal elements. input o f signals during the power off state must be judged separately for each device and according to related specifications governing the device.
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